This invention pertains in general to a semiconductor circuit, and, more particularly, to an electrostatic discharge protection circuit incorporating bi-directional silicon diodes.
A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC. In addition, an ESD event can occur between (a) a pin of the IC and VSS (ground), (b) between a pin and VDD (power), (c) among different pins of the IC, and (d) between VDD and VSS, as shown in FIGS. 1A-1D, respectively. Common sources of ESD include personnel and processing equipment. It is known that the susceptibility of a device to an ESD event may be determined by simulations with one of three models, Human Body Model (HBM), Machines Model (MM) and Charged Device Model (CDM). These models, although do not necessarily simulate the susceptibility of real life situations, are used to establish baselines of susceptibility data.
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program forxe2x80x94Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4, 1999), provides for ESD sensitivity testings for each of the three models. The HBM model represents the discharge from the fingertip of a standing individual delivered to the conductive leads of the device. FIG. 2 shows an HBM model ESD test circuit, modeled by a 100 pF capacitor, representing the effective capacitance of the human body, discharged through a switching component and 1,500 ohm series resistor, representing the effective resistance of the human body, into the device under tests. The discharge is a double exponential waveform with a rise time of 2-10 nanoseconds (nS) and a pulse duration of approximately 150 nS. Similar testing parameters are set forth in MIL-STD-883E method 3015.7 (Mar. 22, 1989), and JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), JESD22-A114-B (June 2000). An example discharge voltage is approximately 2,000 volts at a peak current of approximately 1.33 amperes (A).
The MM model represents a rapid discharge from items such as a charged board assembly, charged cables, or the conduction arm of an automatic tester. The effective capacitance is approximately 200 pF discharged through a 500 nH inductor directly into the device because the effective resistance of the machine is approximately zero. The discharge is a sinusoidal decaying waveform having a peak current of approximately 8 A with a rise time of 5-8 nS and a period of approximately 80 nS. The MM model is also described in EIA/JEDEC Standard, Test Method A115-A for Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM), EIA/JESD22-A115-A (October 1997).
The CDM model is device dependent, and describes a phenomenon when a device acquires charge through frictional or electrostatic induction processes and then abruptly touches a grounded object or surface. The waveform rise time is generally less than 200 picoseconds, and the entire ESD event can take place in less than 2.0 nS. Current levels can reach several tens of amperes during discharge. The CDM model is also described in JEDEC Standard, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components, JESD22-C101-A (June 2000).
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program forxe2x80x94Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4,1999), MIL-STD-883E method 3015.7 (Mar. 22, 1989), JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), JESD22-A114-B (June 2000), EIA/JEDEC Standard, Test Method A115-A for Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM), EIA/JESD22-A115-A (October 1997), and JEDEC Standard, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components, JESD22-C101-A (June 2000) are hereby incorporated by reference.
In commercial applications, a device is expected to withstand xc2x12,000 volts in ESD for HBM models, xc2x1200 volts for MM models, and xc2x11000 volts for CDM models. FIG. 3 is a plot that shows the characteristics of HBM, MM and CDM discharges. As shown in FIG. 3, the CDM discharge reaches a peak current of approximately 15A in less than 1 nS, and the discharge is complete within approximately 10 nS.
Many schemes have been implemented to protect an IC from the three modeled ESD events. A common protection scheme is using a parasitic transistor associated with an n-type metal-oxide semiconductor (MOS) with the source coupled to ground and the drain connected to the pin of the ESD protection device. Diodes or diode-coupled transistors have been used for ESD protection in radio-frequency (RF) applications. In a RF IC, an on-chip ESD circuit should ideally provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency. In a deep-submicron complementary metal-oxide semiconductor (CMOS) process technology with shallow-trench isolations (STIs), a diode has been used for ESD protection and is generally formed contiguous with either an N+ or P+ diffusion region in a semiconductor substrate. FIG. 4A shows a cross-sectional view of a known diode ESD protection structure formed in an IC. Referring to FIG. 4A, a P+ diffusion region is bound by STIs on either side, and therefore the diode formed by the STI is also known as an STI-bound diode. The STI-bound diode exhibits a bottom capacitance, Cbottom. However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P+ diffusion region and the STIs around the P+ region.
FIG. 4B shows a cross-sectional view of another known diode ESD protection structure, known as a polysilicon-bound diode, introduced to address the leakage current problem with an STI-bound diode. The P+ diffusion region in a polysilicon-bound diode is now defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated. However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the addition of the sidewall junction capacitance of the P+ diffusion region.
FIG. 5 is a circuit diagram showing a known ESD protection scheme using dual diodes. Referring to FIG. 5, the combination of the dual-diode structures and VDD-to-VSS ESD clamp circuit provides a path for an ESD current 2 to discharge, instead of through the internal circuits. When ESD current 2 is provided to a signal pad PAD1, and with a signal pad PAD2 relatively grounded, ESD current 2 is conducted to VDD through Dp1. ESD current 2 is discharged to VSS through the VDD-to-VSS ESD clamp circuit and flows out of the IC from Dn2 to PAD2. Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitance of Cn1. The total input capacitance Cin primarily comes from the parasitic junction capacitance of diodes, and is calculated as follows:
Cin=Cp1+Cn1
wherein Cp1 and Cn1 are parasitic junction capacitances of diodes Dp1 and Dn1, respectively.
FIG. 6 is a plot showing the relationship between a pad voltage and parasitic input capacitance of the circuit shown in FIG. 5. Referring to FIG. 6, when the voltage on the pad increases, the parasitic junction capacitance of Dp1 increases and the parasitic junction capacitance of Dn1 decreases. Therefore, the total input parasitic capacitance Cin is nearly constant. This characteristic is important in RF applications. However, the total parasitic capacitance of a polysilicon-bound diode, as compared to an STI-bound diode, is increased because of the addition of a sidewall capacitance, Csidewall, as shown in FIG. 4B.
In accordance with the invention, there is provided an integrated circuit device that includes at least one bi-directional silicon diode having a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, and wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.
In one aspect of the invention, the at least one bi-directional silicon diode includes one or more serially coupled bi-directional silicon diodes.
Also in accordance with the present invention, there is provided an electrostatic discharge protection circuit that includes at least one bi-directional silicon diode having a first silicon-on-insulator diode and a second silicon-on-insulator diode, wherein an n-type portion of the first silicon-on-insulator diode is coupled to a p-type portion of the second silicon-on-insulator diode and a p-type portion of the first silicon-on-insulator diode is coupled to an n-type portion of the second silicon-on-insulator diode, and wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.
Further in accordance with the present invention, there is provided an integrated circuit that includes a signal pad, a first voltage source, and a first electrostatic discharge clamp circuit, coupled to the first voltage source, having at least one bi-directional silicon diode including a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, and wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.
In one aspect of the invention, the first voltage source is VDD, and the first electrostatic discharge clamp circuit is coupled to the signal pad to protect the circuit from at least a human body model electrostatic discharge or machine model electrostatic discharge.
In another aspect of the invention, there also includes a second electrostatic discharge clamp circuit having at least one bi-directional silicon diode including a third silicon diode and a fourth silicon diode, wherein an n-type portion of the third silicon diode is coupled to a p-type portion of the fourth silicon diode and a p-type portion of the third silicon diode is coupled to an n-type portion of the fourth silicon diode, and wherein the second electrostatic discharge clamp circuit is coupled to VDD and a bulk of a first transistor at one end and to a gate of the first transistor at another end to protect the first transistor from at least a charged device model electrostatic discharge.
In yet another aspect of the invention, the first voltage source is VSS, and the first electrostatic discharge clamp circuit is coupled to the signal pad to protect the circuit from at least a human body model electrostatic discharge or machine model electrostatic discharge.
In still another aspect of the invention, the first voltage source is VDD, and the first electrostatic discharge clamp circuit is coupled to a bulk at one end and to a gate at another end of a first transistor to protect the first transistor from at least a charged device model electrostatic discharge.
In another aspect of the invention, there additionally includes a second voltage source coupled to the first electrostatic discharge clamp circuit at a different end than the first voltage source, wherein the first voltage source is VDD and the second voltage source is VSS for providing electrostatic discharge protection.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.